Leading-edge ASICs
The feature-rich M160 ASICs deliver a comprehensive hardware-based system for packet processing, including route lookups, filtering, sampling, rate limiting, load balancing, buffer management, switching, encapsulation, and de-encapsulation functions. To ensure a non-blocking forwarding path, all channels between the ASICs are oversized, dedicated paths.

Internet Processor II ASICs
Each of the four Internet Processor II ASICs (one per SFM) supports a lookup rate of over 40 Mpps. With over one million gates, the Internet Processor II ASIC delivers high-speed forwarding performance with advanced services, such as filtering and sampling, enabled. It is the largest, fastest, and most advanced ASIC ever implemented on a router platform and deployed in the Internet.

Distributed Buffer Manager ASICs
The Distributed Buffer Manager ASICs allocate incoming data packets throughout shared memory on the FPCs. This single-stage buffering improves performance by requiring only one write to and one read from shared memory. There are no extraneous steps of copying packets from input buffers to output buffers. The shared memory is completely nonblocking, which in turn, prevents head-of-line blocking.

I/O Manager ASICs
Each FPC is equipped with an I/O Manager ASIC that supports wire-rate packet parsing, packet prioritizing, and queuing. Each I/O Manager ASIC divides the packets, stores them in shared memory (managed by the Distributed Buffer Manager ASICs), and re-assembles the packets for transmission.

Packet Director ASICs
The Packet Director ASICs balance and distribute packet loads across the four I/O Manager ASICs. Since each SFM represents 40 Mpps of lookup and 40 Gbps of throughput, and since the Packet Director ASICs balance traffic across the I/O Manager ASICs before it is forwarded to the SFM, the aggregate throughput is 160 Gbps.

Media-specific ASICs
The media-specific ASICs perform physical layer functions, such as framing. Each PIC is equipped with an ASIC or FPGA that performs control functions tailored to the PIC's media type.

Packet Forwarding Engine
The PFE provides Layer 2 and Layer 3 packet switching, route lookups, and packet forwarding. The Internet Processor II ASIC forwards up to an aggregate 160 Mpps for all packet sizes. The aggregate throughput is over 160-Gbps half duplex.

The PFE supports the same ASIC-based features supported by all other M-series routers. For example, class-of-service features include rate limiting, classification, priority queuing, Random Early Detection, and Weighted Round Robin to increase bandwidth efficiency. Filtering and sampling are also available for restricting access, increasing security, and analyzing network traffic.

Finally, the PFE delivers maximum stability during exceptional conditions, while also providing a significantly lower part count. This stability reduces power consumption and increases mean time between failure.

Flexible PIC Concentrators
The FPCs house PICs and connect them to the rest of the router so that incoming packets are then forwarded across the midplane to the appropriate destination port. Each FPC slot contains an FPC1, FPC2, or an OC-192c/STM-64 PIC. There are four dedicated 3.2-Gbps full-duplex channels (one per SFM) between each FPC slot and the core of the PFE.

Each FPC contains shared memory for storing data packets received; the Distributed Buffer Manager ASICs on each SFM manage this memory. Each FPC also contains two Packet Director ASICs for sending bytes to each of the four I/O Manager ASICs, also located on the FPC.

Physical Interface Cards
PICs provide a complete range of fiber optic and electrical transmission interfaces to the network. All PICs except the OC-192c/STM-64 occupy one of four PIC spaces in an FPC. The OC-192c/STM-64 PIC occupies an entire FPC slot.

The M160 router offers flexibility and conserves valuable rack space by supporting a wide variety of PICs and port densities. Additionally, it supports the Tunnel Services PIC, which enables the M160 router to function as the ingress or egress point of an IP-IP unicast tunnel, a Cisco generic routing encapsulation (GRE) tunnel, or a Protocol Independent Multicast - Sparse Mode (PIM-SM) tunnel.

Switching and Forwarding Modules
The SFMs perform route lookup, filtering, and sampling, as well as provide switching to the destination FPC. Hosting both the Internet Processor II ASIC and two Distributed Buffer Manager ASICs, the SFM makes forwarding decisions, distributes packets throughout memory, and forwards notification of outgoing packets. There are four SFMs, thus ensuring automatic failover to a redundant SFM in case of failure.
Routing Engine
The Routing Engine maintains the routing tables and controls the routing protocols, as well as the JUNOS software processes that control the router’s interfaces, the chassis components, system management, and user access to the router. These routing and software processes run on top of a kernel that interacts with the PFE.

• The Routing Engine processes all routing protocol updates from the network, so PFE performance is not affected.
  
• The Routing Engine constructs and maintains routing tables with a complete set of Internet features and provides full flexibility for advertising, filtering, and modifying routes. Routing policies are set according to route parameters, such as prefixes, prefix lengths, and BGP attributes.

You can install a redundant Routing Engine to ensure maximum system availability and to minimize MTTR in case of failure. Each Routing Engine requires an adjacent MCS.

JUNOS Internet Software
JUNOS software is optimized to scale to large numbers of network interfaces and routes. The software consists of a series of system processes running in protected memory on top of an independent operating system. The modular design improves reliability by protecting against system-wide failure since the failure of one software process does not affect other processes.