Architecture

The two key components of the architecture are the Packet Forwarding Engine (PFE) and the Routing Engine, which are connected via a 100-Mbps link. Control traffic passing through the 100-Mbps link is prioritized and rate limited to help protect against denial-of-service attacks.

• The PFE is responsible for packet forwarding performance. It consists of the Forwarding Engine Board (FEB), midplane, PICs, and state-of-the-art ASICs.
  
• The Routing Engine maintains the routing tables and controls the routing protocols. It consists of an Intel-based PCI platform running JUNOS software.

The architecture ensures industry-leading service delivery by cleanly separating the forwarding performance from the routing performance. This separation ensures that stress experienced by one component does not adversely affect the performance of the other since there is no overlap of required resources.

Leading-edge ASICs
The feature-rich ASICs deliver a comprehensive hardware-based system for packet processing, including route lookups, filtering, sampling, rate limiting, load balancing, buffer management, switching, encapsulation, and de-encapsulation functions. To ensure a non-blocking forwarding path, all channels between the ASICs are oversized, dedicated paths.

Internet Processor II ASIC
The Internet Processor II ASIC supports a lookup rate of over 40 Mpps. With over one million gates, the Internet Processor II ASIC delivers high-speed forwarding performance with advanced services, such as filtering and sampling, enabled. It is the largest, fastest, and most advanced ASIC ever implemented on a router platform and deployed in the Internet.

Distributed Buffer Manager ASICs
The Distributed Buffer Manager ASICs allocate incoming data packets throughout shared memory on the FEB. This single-stage buffering improves performance by requiring only one write to and one read from shared memory. There are no extraneous steps of copying packets from input buffers to output buffers. The shared memory is completely nonblocking, which in turn, prevents head-of-line blocking.

I/O Manager ASICs
The FEB is equipped with one and two I/O Manager ASICs for the M5 and M10 routers, respectively, for wire-rate packet parsing, packet prioritizing, and queuing. This ASIC divides the packets, stores them in shared memory (managed by the Distributed Buffer Manager ASICs), and re-assembles the packets for transmission.

Media-specific ASICs
The media-specific ASICs perform physical layer functions, such as framing. Each PIC is equipped with an ASIC or FPGA that performs control functions tailored to the PIC's media type.



Packet Forwarding Engine
The PFE provides Layer 2 and Layer 3 packet switching, route lookups, and packet forwarding. The Internet Processor II ASIC forwards up to 40 Mpps for all packet sizes. The aggregate throughput is over 5 Gbps half duplex in an M5 router and over 10 Gbps half duplex in an M10 router.

The PFE supports the same ASIC-based features supported by all other M-series routers. For example, class-of-service features include rate limiting, classification, priority queuing, Random Early Detection, and Weighted Round Robin to increase bandwidth efficiency. Filtering and sampling are also available for restricting access, increasing security, and analyzing network traffic.

Finally, the PFE delivers maximum stability during exceptional conditions, while also providing a significantly lower part count. This stability reduces power consumption and increases mean time between failure.

Forwarding Engine Board
The FEB performs route lookup, filtering, and sampling, as well as provides switching to the destination PIC. Hosting the Internet Processor II ASIC, two Distributed Buffer Manager ASICs, and two I/O Manager ASICs, the FEB is responsible for making forwarding decisions, distributing packets throughout memory, and forwarding notification of outgoing packets.

Physical Interface Cards
PICs provide a complete range of fiber optic and electrical transmission interfaces to the network. The M5 router holds four PICs, and the M10 router holds eight. All PICs occupy a single PIC space connected to the FEB.

Additionally, the routers support the Tunnel Services PIC, which enables them to function as the ingress or egress point of an IP-IP unicast tunnel, a Cisco generic routing encapsulation (GRE) tunnel, or a Protocol Independent Multicast - Sparse Mode (PIM-SM) tunnel.

Routing Engine
The Routing Engine maintains the routing tables and controls the routing protocols, as well as the JUNOS software processes that control the router’s interfaces, the chassis components, system management, and user access to the router. These routing and software processes run on top of a kernel that interacts with the PFE.

• The Routing Engine processes all routing protocol updates from the network, so PFE performance is not affected.
  
• The Routing Engine constructs and maintains routing tables with a complete set of Internet features and provides full flexibility for advertising, filtering, and modifying routes. Routing policies are set according to route parameters, such as prefixes, prefix lengths, and BGP attributes.

JUNOS Internet Software
JUNOS software is optimized to scale to large numbers of network interfaces and routes. The software consists of a series of system processes running in protected memory on top of an independent operating system. The modular design improves reliability by protecting against system-wide failure since the failure of one software process does not affect other processes.